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Creators/Authors contains: "Yoo, Hocheon"

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  1. Free, publicly-accessible full text available April 1, 2026
  2. Abstract Probabilistic inference in data-driven models is promising for predicting outputs and associated confidence levels, alleviating risks arising from overconfidence. However, implementing complex computations with minimal devices still remains challenging. Here, utilizing a heterojunction of p- and n-type semiconductors coupled with separate floating-gate configuration, a Gaussian-like memory transistor is proposed, where a programmable Gaussian-like current-voltage response is achieved within a single device. A separate floating-gate structure allows for exquisite control of the Gaussian-like current output to a significant extent through simple programming, with an over 10000 s retention performance and mechanical flexibility. This enables physical evaluation of complex distribution functions with the simplified circuit design and higher parallelism. Successful implementation for localization and obstacle avoidance tasks is demonstrated using Gaussian-like curves produced from Gaussian-like memory transistor. With its ultralow-power consumption, simplified design, and programmable Gaussian-like outputs, our 3-terminal Gaussian-like memory transistor holds potential as a hardware platform for probabilistic inference computing. 
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    Free, publicly-accessible full text available December 1, 2025
  3. Abstract Reinforcement learning (RL) relies on Gaussian and sigmoid functions to balance exploration and exploitation, but implementing these functions in hardware typically requires iterative computations, increasing power and circuit complexity. Here, Gaussian‐sigmoid reinforcement transistors (GS‐RTs) are reported that integrate both activation functions into a single device. The transistors feature a vertical n‐p‐i‐p heterojunction stack composed of a‐IGZO and DNTT, with asymmetric source–drain contacts and a parylene interlayer that enables voltage‐tunable transitions between sigmoid, Gaussian, and mixed responses. This architecture emulates the behavior of three transistors in one, reducing the required circuit complexity from dozens of transistors to fewer than a few. The GS‐RT exhibits a peak current of 5.95 µA at VG= −17 V and supports nonlinear transfer characteristics suited for neuromorphic computing. In a multi‐armed bandit task, GS‐RT‐based RL policies demonstrate 20% faster convergence and 30% higher final reward compared to conventional sigmoid‐ or Gaussian‐based approaches. Extending this advantage further, GS‐RT‐based activation function in deep RL for cartpole balancing significantly outperforms the traditional ReLU‐based activation function in terms of faster learning and tolerance to input perturbations. 
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  4. Abstract To achieve the high energy densities demanded by emerging technologies, lithium battery electrodes need to approach the volumetric and specific capacity limits of their electrochemically active constituents, which requires minimization of the inactive components of the electrode. However, a reduction in the percentage of inactive conductive additives limits charge transport within the battery electrode, which results in compromised electrochemical performance. Here, an electrode design that achieves efficient electron and lithium‐ion transport kinetics at exceptionally low conductive additive levels and industrially relevant active material areal loadings is introduced. Using a scalable Pickering emulsion approach, Ni‐rich LiNi0.8Co0.15Al0.05O2(NCA) cathode powders are conformally coated using only 0.5 wt% of solution‐processed graphene, resulting in an electrical conductivity that is comparable to 5 wt% carbon black. Moreover, the conformal graphene coating mitigates degradation at the cathode surface, thus providing improved electrochemical cycle life. The morphology of the electrodes also facilitates rapid lithium‐ion transport kinetics, which provides superlative rate capability. Overall, this electrode design concurrently approaches theoretical volumetric and specific capacity limits without tradeoffs in cycle life, rate capability, or active material areal loading. 
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